Hello, this is Homcorn from ITLover0.tech and today’s post is going to be about the 3D Monolithic Integration analysis, in regards to the 3D IC (Three-dimensional integrated circuit) and why Lisa Su is such a genius.
This post was originally written by GENo07 through perplexity.
Intro: the combination of 3D IC and mathematics
The semi-conductor industry has been following the ‘Moore’s law’ for a long time. However, as the reduction in the horizontal plane of the semi-conductors reached its physical limits, an expansion towards the vertical plane rose as its new breakthrough. In order for the 3D IC to be properly designed, is it crucial to implement complicating mathematical modellings.
Major Aspects of Mathematical Modelling
1. Structural Analysis Modelling
The basis to structural analysis modelling is the FEM (finite element method). This is done by converting the infinite amounts of nodal points and degrees of freedom to a finite amount, and expressing it in a linear system. The main points of the structural analysis are ‘Poisson’s Ratio’, ‘CTE
(Coefficient of thermal expansion)’, and stress.
2.Electrical Modelling
Poisson’s equation is the key point.
In here, the Laplacian operator (∇2) can be expanded like this in a three-dimentional space.
These equations can be used in these areas:
- Understanding electric charge distribution and electrical field in a three-dimentional space
- Calculating the electric potential and electrical field near the TSV (through-silicon via)
- Modelling the MOS (Metal-oxide-semiconductor) structure between the TSV and Silicon Wafer
3. Thermal Analysis Modelling
Analyzes the temperature at major points through definition:
- Ambient Temperature (Ta)
- Junction Temperature (Tj)
- Case Temperature (Tc)
- Board Temperature (Tb)
4. Additive Manufacturing Modelling
Integral equation used to calculate curvature length:
s(t) = ∫0tx ⋅ ((u)+y) ⋅ ((u)+z) ⋅ (u)dus(t) = ∫0tx ⋅ ((u)+y) ⋅ ((u)+z) ⋅ (u)du
Real Life Application
AMD’s Innovation
AMD was able to vertically stack the cache memories on top of the CPU Die using the 3D V-Cache technology. A vertical connection through the TSV was crucial in this process, which required complicated electrical modelling.
Samsung’s V-NAND
The V-NAND is modelled up to the 236th layer, showing its success in mathematical modelling. In order to minimize interference between the layers, the understanding of the magnetic field was the most important aspect.
Future Tasks and Prospects
Technical Tasks
- Problems with heat management
- Increased heating value due to vertical stacking
- Requires new cooling solution
- Reliability Test
- Analyze junction strength between layers
- Thermal stress simulation
Future Prospects
- Intel: Aims for 1 trillion transistor per package by 2030
- TSMC: Development of advanced packaging and 3D IC technology
- AMD: Application of 3D V-Cache in various areas
Conclusion
The 3D IC technology is not only a physical layering method, but a complex combination of mathematical theories. This technology will continue to improve further in the future, and at is core will be mathematical modelling. In our next post, we will be talking about specific value analysis for reliability verification tests.
